Invention Grant
- Patent Title: Self-aligned double patterning process and semiconductor structure formed using thereof
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Application No.: US17075875Application Date: 2020-10-21
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Publication No.: US11676822B2Publication Date: 2023-06-13
- Inventor: Yu-Wen Wang , Kuo-Chyuan Tzeng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/3213 ; H01L21/308 ; H01L21/768 ; H01L21/311

Abstract:
A method for fabrication of a semiconductor structure according to some embodiments of the present disclosure comprises following steps. A first mandrel is formed over a target layer over a substrate, wherein the first mandrel comprises a mandrel island connecting a first mandrel strip and a second mandrel strip. A first spacer is formed along first and second sidewalls of the mandrel island, the first mandrel strip, and the second mandrel strip. The first mandrel is then removed, and the target layer is patterned with the first spacer remains over the target layer. The first mandrel strip and the second mandrel strip are misaligned from one another.
Public/Granted literature
- US20210035809A1 SELF-ALIGNED DOUBLE PATTERNING PROCESS AND SEMICONDUCTOR STRUCTURE FORMED USING THEREOF Public/Granted day:2021-02-04
Information query
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