Resistance tunable fuse structure formed by embedded thin metal layers
Abstract:
A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse contacts in the fuse stack structure.
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