Invention Grant
- Patent Title: Method of fabricating semiconductor device having void in bit line contact plug
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Application No.: US17482456Application Date: 2021-09-23
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Publication No.: US11678479B2Publication Date: 2023-06-13
- Inventor: Shi-Wei He , Te-Hao Huang , Hsien-Shih Chu , Yun-Fan Chou , Feng-Ming Huang
- Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicant Address: CN Quanzhou
- Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee Address: CN Quanzhou
- Agent Winston Hsu
- Priority: CN 1910877052.X 2019.09.17
- The original application number of the division: US16635465
- Main IPC: H10B12/00
- IPC: H10B12/00

Abstract:
A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.
Public/Granted literature
- US20220013528A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2022-01-13
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