Invention Grant
- Patent Title: Memory arrays and methods used in forming a memory array
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Application No.: US17160956Application Date: 2021-01-28
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Publication No.: US11678483B2Publication Date: 2023-06-13
- Inventor: Bharat Bhushan , Chris M. Carlson , Collin Howder
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- The original application number of the division: US16277311 2019.02.15
- Main IPC: H01L27/11556
- IPC: H01L27/11556 ; H10B41/27 ; G11C8/14 ; G11C16/04 ; G06F3/06 ; H10B41/35 ; H10B41/41 ; H10B41/60 ; H10B43/27 ; H10B43/35 ; H10B43/40

Abstract:
A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.
Public/Granted literature
- US20210151454A1 Memory Arrays And Methods Used In Forming A Memory Array Public/Granted day:2021-05-20
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