Hardware accelerator for integral image computation
Abstract:
A hardware accelerator for computing integral image values of an image is provided that includes a plurality of row computation components configurable to operate in parallel to compute row sum values of respective rows of a row block of the image. The hardware accelerator is further configured to compute integral image values for the row block using the row sum values and block pivots.
Public/Granted literature
Information query
Patent Agency Ranking
0/0