Invention Grant
- Patent Title: Multiple stack high voltage circuit for memory
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Application No.: US17460938Application Date: 2021-08-30
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Publication No.: US11682433B2Publication Date: 2023-06-20
- Inventor: Perng-Fei Yuh , Meng-Sheng Chang , Tung-Cheng Chang , Yih Wang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Foley & Lardner LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C5/14 ; G11C7/10 ; G11C17/18 ; G11C17/16

Abstract:
One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N N MOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.
Public/Granted literature
- US20230066618A1 MULTIPLE STACK HIGH VOLTAGE CIRCUIT FOR MEMORY Public/Granted day:2023-03-02
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