Invention Grant
- Patent Title: Bump-on-trace interconnect
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Application No.: US17102073Application Date: 2020-11-23
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Publication No.: US11682651B2Publication Date: 2023-06-20
- Inventor: Chen-Hua Yu , Chen-Shien Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- The original application number of the division: US13653618 2012.10.17
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L25/00

Abstract:
Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.
Public/Granted literature
- US20210074673A1 Bump-on-Trace Interconnect Public/Granted day:2021-03-11
Information query
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