Invention Grant
- Patent Title: Semiconductor device with isolation layer
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Application No.: US17450200Application Date: 2021-10-07
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Publication No.: US11682725B2Publication Date: 2023-06-20
- Inventor: Fei Zhou
- Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee Address: CN Shanghai; CN Beijing
- Agency: Anova Law Group, PLLC
- Priority: CN 1811287076.1 2018.10.31
- The original application number of the division: US16572882 2019.09.17
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/66 ; H01L21/266 ; H01L21/3213 ; H01L21/02
Abstract:
A semiconductor device is provided. The semiconductor device includes a base substrate; a first well region and a second well region in the base substrate; a gate electrode structure, sidewall spacers, a doped source layer and a doped drain layer over the base substrate; a dielectric layer on the base substrate; and an isolation layer in the dielectric layer. The dielectric layer covers sidewalls of the sidewall spacers, the doped source layer and the doped drain layer, and exposes a top surface of the gate electrode structure. The isolation layer is in the gate electrode structure of the second well region and the base substrate of the second well region, and adjacent to the sidewalls of the sidewall spacer over the second well region.
Public/Granted literature
- US20220029014A1 SEMICONDUCTOR DEVICE WITH ISOLATION LAYER Public/Granted day:2022-01-27
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