- Patent Title: Circuit architecture and layout for a voting interlocked logic cell
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Application No.: US17803280Application Date: 2022-04-18
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Publication No.: US11683040B1Publication Date: 2023-06-20
- Inventor: Klas Olof Lilja
- Applicant: Klas Olof Lilja
- Applicant Address: US CA Pleasanton
- Assignee: Klas Olof Lilja
- Current Assignee: Klas Olof Lilja
- Current Assignee Address: US CA Pleasanton
- Main IPC: H03K19/1776
- IPC: H03K19/1776 ; H03K19/17736 ; H03K19/17784 ; H03K19/23 ; G06F30/392 ; G06F30/398

Abstract:
This invention comprises an integrated circuit in CMOS technology which can act as a regular sequential logic latch, having one data signal input, or as a voting latch, having three data signal inputs. The circuit schematic of this integrated circuit is such that it allows for a certain placement of the devices in the physical, manufactured integrated circuit that makes it possible to optimize the arrangement of the n-type MOSFET devices and p-type MOSFET devices in the circuit independently, using the Layout Optimization through Error Aware Positioning (LEAP), and thereby to remove, or reduce, the occurrence of radiation generated soft errors.
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