Invention Grant
- Patent Title: Co-scheduled loads in a data processing apparatus
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Application No.: US17754739Application Date: 2020-09-28
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Publication No.: US11693665B2Publication Date: 2023-07-04
- Inventor: Mbou Eyole , Michiel Willem Van Tol
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Priority: GB 14923 2019.10.15
- International Application: PCT/GB2020/052343 2020.09.28
- International Announcement: WO2021/074585A 2021.04.22
- Date entered country: 2022-04-11
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38

Abstract:
A data processing apparatus and method of operating such is disclosed. Issue circuitry buffers operations prior to execution until operands are available in a set of registers. A first and a second load operation are identified in the issue circuitry, when both are dependent on a common operand, and when the common operand is available in the set of registers. Load circuitry has a first address generation unit to generate a first address for the first load operation and a second address generation unit to generate a second address for the second load operation. An address comparison unit compares the first address and the second address. The load circuitry is arranged to cause a merged lookup to be performed in local temporary storage, when the address comparison unit determines that the first and the second address differ by less than a predetermined address range characteristic of the local temporary storage.
Public/Granted literature
- US20230064455A1 CO-SCHEDULED LOADS IN A DATA PROCESSING APPARATUS Public/Granted day:2023-03-02
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