Invention Grant
- Patent Title: Caching or evicting host-resident translation layer based on counter
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Application No.: US16947851Application Date: 2020-08-20
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Publication No.: US11693781B2Publication Date: 2023-07-04
- Inventor: Dionisio Minopoli , Daniele Balluchi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F12/0866
- IPC: G06F12/0866

Abstract:
A processing device in a memory system receives, from a host system, a read command comprising an indication of a sub-region of a logical address space of a memory device. The processing device increments a counter associated with a region of the logical address space, the region comprising a plurality of sub-regions including the sub-region, the counter to track a number of read operations performed on the plurality of sub-regions of the region, wherein the counter is periodically decremented in response to an occurrence of a recency event on the memory device. The processing device further determines whether a value of the counter satisfies a cacheable threshold criterion and, responsive to the value of the counter satisfying the cacheable threshold criterion, sends, to the host system, a recommendation to activate the sub-region.
Public/Granted literature
- US20220058134A1 MEMORY ACCESS TRACKING FOR HOST-RESIDENT TRANSLATION LAYER Public/Granted day:2022-02-24
Information query
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