The present application provides a display panel. The display panel includes: gate driver on array (GOA) units arranged along a first direction; clock signal lines arranged along a second direction and arranged at one side of the GOA units; the connection lines, each of the connection lines being extended along the second direction and connected between the corresponding clock signal line and the corresponding GOA units; and a first electrode arranged at one side of the GOA units, the clock signal lines, and the connection lines. The first electrode includes an opening, and the opening is arranged corresponding to at least one of the clock signal lines and/or at least one of the connection lines.