Invention Grant
- Patent Title: Hybrid fine line spacing architecture for bump pitch scaling
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Application No.: US16363688Application Date: 2019-03-25
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Publication No.: US11694898B2Publication Date: 2023-07-04
- Inventor: Suddhasattwa Nad , Jeremy Ecton , Bai Nie , Rahul Manepalli , Marcel Wall
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G09G3/20
- IPC: G09G3/20 ; H01L21/28 ; H01L21/48 ; H01L23/00

Abstract:
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.
Public/Granted literature
- US20200312665A1 HYBRID FINE LINE SPACING ARCHITECTURE FOR BUMP PITCH SCALING Public/Granted day:2020-10-01
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