Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.