Invention Grant
- Patent Title: Multi-level memristor elements
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Application No.: US17308695Application Date: 2021-05-05
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Publication No.: US11696452B2Publication Date: 2023-07-04
- Inventor: John Paul Lesso , Gordon James Bates
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: GB Edinburgh
- Assignee: Cirrus Logic, Inc.
- Current Assignee: Cirrus Logic, Inc.
- Current Assignee Address: US TX Austin
- Agency: Jackson Walker L.L.P.
- Priority: GB 07685 2019.05.30
- Main IPC: G11C11/00
- IPC: G11C11/00 ; H10B61/00 ; G06N3/02 ; G11C11/16 ; H10N50/10
Abstract:
There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.
Public/Granted literature
- US20210257405A1 MULTI-LEVEL MEMRISTOR ELEMENTS Public/Granted day:2021-08-19
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