Invention Grant
- Patent Title: Test method and system for testing connectivity of semiconductor structure
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Application No.: US17650849Application Date: 2022-02-12
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Publication No.: US11698409B2Publication Date: 2023-07-11
- Inventor: Geyan Liu
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Syncoda LLC
- Agent Feng Ma
- Priority: CN 2110831423.8 2021.07.22
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/26

Abstract:
A test method for testing connectivity of a semiconductor structure includes operations as follows. A semiconductor structure and a detection transistor are provided. The semiconductor structure includes a through silicon via structure having a first terminal and a second terminal arranged to be opposite. An intrinsic conductivity factor of the detection transistor is obtained. The detection transistor is turned on upon receiving a test signal, and a test voltage is provided to the second terminal, to enable the detection transistor to operate in a deep triode region, and a current flowing through the second terminal is obtained during operation of the detection transistor in the deep triode region. A resistance of the through silicon via structure is obtained based on the intrinsic conductivity factor, an operating voltage, the test voltage, and the current flowing through the second terminal.
Public/Granted literature
- US20230029337A1 TEST METHOD AND SYSTEM FOR TESTING CONNECTIVITY OF SEMICONDUCTOR STRUCTURE Public/Granted day:2023-01-26
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