Invention Grant
- Patent Title: Circuit arrangements having reduced dependency on layout environment
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Application No.: US17393188Application Date: 2021-08-03
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Publication No.: US11699015B2Publication Date: 2023-07-11
- Inventor: Huaixin Xian , J. B. Zhang , Yang Zhou , Kai Zhou , Qingchao Meng , Lei Pan
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC CHINA COMPANY, LIMITED , TSMC NANJING COMPANY, LIMITED
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,TSMC NANJING COMPANY, LIMITED,TSMC CHINA COMPANY, LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,TSMC NANJING COMPANY, LIMITED,TSMC CHINA COMPANY, LIMITED
- Current Assignee Address: TW Hsinchu; CN Nanjing; CN Shanghai
- Agency: Hauptman Ham, LLP
- Priority: CN 2110752564.0 2021.07.02
- Main IPC: G06F30/00
- IPC: G06F30/00 ; G06F30/392 ; G06F30/30 ; G06F119/18

Abstract:
An integrated circuit includes a middle active-region structure between a group-one active-region structure and a group-two active-region structure. The integrated circuit also includes a main circuit, a group-one circuit, and a group-two circuit. The main circuit includes at least one boundary gate-conductor intersecting the middle active-region structure. The group-one circuit includes a group-one isolation structure separating the group-one active-region structure into a first part in the group-one circuit and a second part in a first adjacent circuit. The group-two circuit includes a group-two isolation structure separating the group-two active-region structure into a first part in the group-two circuit and a second part in a second adjacent circuit.
Public/Granted literature
- US20230004702A1 CIRCUIT ARRANGEMENTS HAVING REDUCED DEPENDENCY ON LAYOUT ENVIRONMENT Public/Granted day:2023-01-05
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