Control logic in a memory device identifies a first plurality of groups of programming distributions, wherein each group comprises a subset of programming distributions associated with a portion of a memory array of the memory device configured as quad-level (QLC) memory. During a first pass of a multi-pass programming operation, the control logic coarsely programs memory cells in the portion configured as QLC memory to initial values representing a second plurality of pages of host data and stores, in a portion of the memory array of the memory device configured as single-level cell (SLC) memory, an indicator of the first plurality of groups of programming distributions with which each of the coarsely programmed memory cells is associated. During a second pass of the multi-pass programming operation, the control logic reads the coarsely programmed initial values from the first pass based on the indicator of the first plurality of groups of programming distributions and finely programs the memory cells in the portion configured as QLC memory to final values representing the second plurality of pages of host data.