Invention Grant
- Patent Title: Integrated circuit die stacked with backer die including capacitors and thermal vias
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Application No.: US17213974Application Date: 2021-03-26
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Publication No.: US11699629B2Publication Date: 2023-07-11
- Inventor: Anthony Chiu , Bror Peterson , Andrew Ketterson
- Applicant: Qorvo US, Inc.
- Applicant Address: US NC Greensboro
- Assignee: Qorvo US, Inc.
- Current Assignee: Qorvo US, Inc.
- Current Assignee Address: US NC Greensboro
- Agency: Withrow & Terranova, P.L.L.C.
- Main IPC: H01L23/367
- IPC: H01L23/367 ; H01L23/373 ; H01L25/18 ; H01L23/48 ; H01L23/66 ; H01L23/00 ; H01L49/02

Abstract:
The disclosure is directed to an integrated circuit (IC) die stacked with a backer die, including capacitors and thermal vias. The backer die includes a substrate material to contain and electrically insulate one or more capacitors at a back of the IC die. The backer die further includes a thermal material that is more thermally conductive than the substrate material for thermal spreading and increased heat dissipation. In particular, the backer die electrically couples capacitors to the IC die in a stacked configuration while also spreading and dissipating heat from the IC die. Such a configuration reduces an overall footprint of the electronic device, resulting in decreased integrated circuits (IC) packages and module sizes. In other words, instead of placing the capacitors next to the IC die, the capacitors are stacked on top of the IC die, thereby reducing an overall surface area of the package.
Public/Granted literature
- US20220310471A1 INTEGRATED CIRCUIT DIE STACKED WITH BACKER DIE INCLUDING CAPACITORS AND THERMAL VIAS Public/Granted day:2022-09-29
Information query
IPC分类: