Invention Grant
- Patent Title: Memory sub-systems including memory devices of various latencies and capacities
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Application No.: US16933755Application Date: 2020-07-20
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Publication No.: US11704057B2Publication Date: 2023-07-18
- Inventor: Luca Bert
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/1009

Abstract:
A write request comprising a logical address, a payload, and an indicator reflecting the character of the payload is received from an application. Based on the indicator, a value of a parameter associated with storing the payload on one or more of a plurality of memory devices is identified. The value of the parameter is determined to satisfy a criterion associated with a particular memory device of the plurality of memory devices. The payload is stored on the particular memory device.
Public/Granted literature
- US20220019379A1 MEMORY SUB-SYSTEMS INCLUDING MEMORY DEVICES OF VARIOUS LATENCIES AND CAPACITIES Public/Granted day:2022-01-20
Information query