- Patent Title: Fully self-aligned via with selective bilayer dielectric regrowth
-
Application No.: US17223831Application Date: 2021-04-06
-
Publication No.: US11705369B2Publication Date: 2023-07-18
- Inventor: Kandabara Tapily , Jeffrey Smith
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- The original application number of the division: US16453473 2019.06.26
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522

Abstract:
A semiconductor device includes conductive structures formed in a first dielectric layer, a conductive cap layer selectively positioned over the conductive structures and the first dielectric layer with a top surface and sidewalls, a second dielectric layer selectively positioned over the first dielectric layer and disposed between the sidewalls of the conductive cap layer, a third dielectric layer selectively positioned over the second dielectric layer and disposed between the sidewalls of the conductive cap layer, a fourth dielectric layer arranged over the conductive structures and the third dielectric layer, and an interconnect structure formed in the fourth dielectric layer. The interconnect structure includes a trench structure and a via structure that is positioned below the trench structure and connected to the trench structure. The via structure includes a first portion positioned over the conductive cap layer and a second portion disposed over the first portion and the third dielectric layer.
Public/Granted literature
- US20210249305A1 FULLY SELF-ALIGNED VIA WITH SELECTIVE BILAYER DIELECTRIC REGROWTH Public/Granted day:2021-08-12
Information query
IPC分类: