Invention Grant
- Patent Title: Self-aligned gate endcap (SAGE) architecture having local interconnects
-
Application No.: US16294380Application Date: 2019-03-06
-
Publication No.: US11705453B2Publication Date: 2023-07-18
- Inventor: Sairam Subramanian , Walid M. Hafez , Sridhar Govindaraju , Kiran Chikkadi
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/78 ; H01L29/66 ; H01L21/8238 ; H01L23/528 ; H01L21/768 ; H01L21/308 ; H01L23/00

Abstract:
Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.
Public/Granted literature
- US20200286891A1 SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING LOCAL INTERCONNECTS Public/Granted day:2020-09-10
Information query
IPC分类: