A control circuit for a power factor correction (PFC) circuit, the control circuit includes a multiplier having first, second, and third multiplier inputs and a multiplier output. The control circuit has an adder having first and second inputs and an output. The first input of the adder is coupled to the multiplier output. The control circuit further includes a root mean square (RMS) calculation circuit configured to determine a square of a root mean square of an input sinusoidal voltage. The RMS calculation circuit has an output coupled to the second multiplier input. An input voltage square calculation circuit is configured to determine a square of the input sinusoidal voltage. The input voltage square calculation circuit has an output coupled to the third multiplier input.