Invention Grant
- Patent Title: Method for manufacturing semiconductor memory device
-
Application No.: US17546657Application Date: 2021-12-09
-
Publication No.: US11706913B2Publication Date: 2023-07-18
- Inventor: Hao-Chan Lo , Hsing-Han Wu , Jr-Chiuan Wang , Jen-I Lai , Chun-Heng Wu
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H10B12/00

Abstract:
The present disclosure provides to a method for manufacturing a semiconductor memory device. The method includes receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing pad to form an inclined surface connecting a top surface of the landing pad to a sidewall of the landing pad; etching the nitride layer of the first bit line structure and the spacer nitride layer from the top opening so as to form a concavity;
etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.
etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.
Public/Granted literature
- US20230189507A1 METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2023-06-15
Information query
IPC分类: