Invention Grant
- Patent Title: Method of forming an array boundary structure to reduce dishing
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Application No.: US17555828Application Date: 2021-12-20
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Publication No.: US11706914B2Publication Date: 2023-07-18
- Inventor: Meng-Han Lin , Te-Hsin Chiu , Wei-Cheng Wu , Li-Feng Teng , Chien-Hung Chang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- The original application number of the division: US16022702 2018.06.29
- Main IPC: H01L21/765
- IPC: H01L21/765 ; H10B20/00 ; H01L21/28 ; H01L21/762 ; H01L23/00 ; H01L29/06 ; H01L29/40 ; H01L29/66 ; H10B41/35 ; H10B41/43 ; H10B41/49

Abstract:
A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
Public/Granted literature
- US20220115391A1 ARRAY BOUNDARY STRUCTURE TO REDUCE DISHING Public/Granted day:2022-04-14
Information query
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