Invention Grant
- Patent Title: Mask optimization process
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Application No.: US17838681Application Date: 2022-06-13
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Publication No.: US11714349B2Publication Date: 2023-08-01
- Inventor: Daniel Beylkin , Sagar Vinodbhai Trivedi
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: G03F1/70
- IPC: G03F1/70 ; G03F1/36

Abstract:
A method performed by a computing system includes receiving a layout pattern, receiving a target pattern associated with the layout pattern, receiving a set of constraints related to the target pattern, simulating a first contour associated with the layout pattern, determining a first difference between the first contour and the target pattern, simulating a second contour associated with a modified layout pattern, and determining a second difference between the second contour and a modified target pattern. The modified target pattern is different than the target pattern and within the constraints. The method further includes fabricating a mask having the final layout pattern.
Public/Granted literature
- US20220326604A1 Mask Optimization Process Public/Granted day:2022-10-13
Information query
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