Clock control to increase robustness of a serial bus interface
Abstract:
An electronic control unit (ECU) includes a processor, a Controller Area Network (CAN) controller, clock gating logic, and security gating logic. The CAN controller having a status and configured to receive data and control signals from the processor, and a clock signal, package the data to create a CAN protocol frame held in at least one transmit buffer, and shift the CAN protocol frame to a CAN transceiver that is configured to transmit the CAN protocol frame to a CAN bus. The security gating logic configured to, in response to the status of the CAN controller being active, inhibit disabling the clock signal.
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