Invention Grant
- Patent Title: Block budget enhancement mechanisms for memory
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Application No.: US17530056Application Date: 2021-11-18
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Publication No.: US11714565B2Publication Date: 2023-08-01
- Inventor: Bhanushankar Doni , Raghavendra Gopalkrishnan
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Michael Best & Friedrich LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F3/06
Abstract:
A data storage device, in one implementation, includes a memory device having Single Level Cell (SLC) blocks and Multi-Level Cell (MLC) blocks, such as Triple Level Cell (TLC) blocks. If a SLC block is determined to have errors, the SLC block is reallocated as a TLC block. In some implementations, the TLC block is used to store TLC cold data.
Public/Granted literature
- US20230152995A1 BLOCK BUDGET ENHANCEMENT MECHANISMS FOR MEMORY Public/Granted day:2023-05-18
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