Invention Grant
- Patent Title: Adder circuit using lookup tables
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Application No.: US17134838Application Date: 2020-12-28
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Publication No.: US11714607B2Publication Date: 2023-08-01
- Inventor: Christopher LaFrieda , Virantha Ekanayake
- Applicant: Achronix Semiconductor Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Achronix Semiconductor Corporation
- Current Assignee: Achronix Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F7/575
- IPC: G06F7/575 ; G06F7/504 ; G06F1/03 ; H03K19/20 ; H03K19/21

Abstract:
A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.
Public/Granted literature
- US20220206758A1 ADDER CIRCUIT USING LOOKUP TABLES Public/Granted day:2022-06-30
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