An information handling system includes a dual in-line memory module (DIMM) and a memory controller coupled to the DIMM via a data bus. The memory controller determines that a first lane of a byte group of the data bus is more susceptible to crosstalk than a second lane of the byte group, determines a first performance level of the first lane, changes a delay (D) of a third lane of the byte group, the third lane being adjacent to the first lane, and determines that a second performance level of the first lane is different from the first performance level in response to delaying the third lane.