Invention Grant
- Patent Title: Method of correcting errors in a memory array and method of screening weak bits in the same
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Application No.: US17703857Application Date: 2022-03-24
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Publication No.: US11714717B2Publication Date: 2023-08-01
- Inventor: Yu-Der Chih , Chia-Fu Lee , Chien-Yin Liu , Yi-Chun Shih , Kuan-Chun Chen , Hsueh-Chih Yang , Shih-Lien Linus Lu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/29 ; H03M13/15 ; H03M13/19 ; G11C29/42

Abstract:
A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.
Public/Granted literature
- US20220214943A1 METHOD OF CORRECTING ERRORS IN A MEMORY ARRAY AND METHOD OF SCREENING WEAK BITS IN THE SAME Public/Granted day:2022-07-07
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