Invention Grant
- Patent Title: Compiler flow logic for reconfigurable architectures
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Application No.: US17326128Application Date: 2021-05-20
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Publication No.: US11714780B2Publication Date: 2023-08-01
- Inventor: David Alan Koeplinger , Raghu Prabhakar , Sumti Jairath
- Applicant: SambaNova Systems, Inc.
- Applicant Address: US CA Palo Alto
- Assignee: SambaNova Systems, Inc.
- Current Assignee: SambaNova Systems, Inc.
- Current Assignee Address: US CA Palo Alto
- Agency: Flagship Patents
- Agent Sikander Khan; Bruce Young
- Main IPC: G06F15/78
- IPC: G06F15/78 ; G06F16/901 ; G06F8/41 ; G06F12/02

Abstract:
The technology disclosed partitions a dataflow graph of a high-level program into memory allocations and execution fragments. The memory allocations represent creation of logical memory spaces in on-processor and/or off-processor memories for data required to implement the dataflow graph. The execution fragments represent operations on the data. The technology disclosed designates the memory allocations to virtual memory units and the execution fragments to virtual compute units. The technology disclosed partitions the execution fragments into memory fragments and compute fragments, and assigns the memory fragments to the virtual memory units and the compute fragments to the virtual compute units. The technology disclosed then allocates the virtual memory units to physical memory units and the virtual compute units to physical compute units. It then places the physical memory units and the physical compute units onto positions in the array of configurable units and routes data and control networks between the placed positions.
Public/Granted literature
- US20210271630A1 Compiler Flow Logic for Reconfigurable Architectures Public/Granted day:2021-09-02
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