Invention Grant
- Patent Title: Method and layout of an integrated circuit
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Application No.: US17750201Application Date: 2022-05-20
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Publication No.: US11714947B2Publication Date: 2023-08-01
- Inventor: Mahantesh Hanchinal , Shu-Yi Ying , Chi Wei Hu , Min-Yuan Tsai
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- The original application number of the division: US15355206 2016.11.18
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06F30/398 ; G06F30/3953 ; G06F30/3947 ; G03F1/36 ; H01L21/027 ; H01L21/768 ; H01L21/76 ; G06F119/18

Abstract:
A method of manufacturing an integrated circuit includes adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first and second pair of conductive patterns on the corresponding first and second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and a second set of conductive structures based on the second pair of conductive patterns. A first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. One spacing of a first set of spacings is different from another spacing of the first set of spacings.
Public/Granted literature
- US20220284165A1 METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT Public/Granted day:2022-09-08
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