Invention Grant
- Patent Title: Automated timing closure on circuit designs
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Application No.: US17382621Application Date: 2021-07-22
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Publication No.: US11714950B2Publication Date: 2023-08-01
- Inventor: Veeresh Pratap Singh , Meghraj Kalase , John Blaine , Srinivasan Dasasathyan , Padmini Gopalakrishnan , Frederic Revenu , Veena Johar , Pawan Kumar Singh , Mohit Sharma , Kameshwar Chandrasekar
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Crawford Maunu PLLC
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06F30/398 ; G06F30/327 ; G06F30/31

Abstract:
Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.
Public/Granted literature
- US20230034736A1 AUTOMATED TIMING CLOSURE ON CIRCUIT DESIGNS Public/Granted day:2023-02-02
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