A driving circuit that includes a timing controller, a selecting module connected to the timing controller, and a level shifter connected to the selecting module, wherein the timing controller includes N pins, each of the pins provides a clock signal, and N is a positive integer; the selecting module includes N selecting units, an input terminal of each of the selecting units is connected to a corresponding pin of the timing controller, output terminals of each of the selecting units are connected to M input pins of the level shifter, and M is greater than or equal to 2. The driving circuit according to the present invention individually passes clock signals of a timing controller through selecting units and outputs to a level shifter, and pins of the timing controller can be substantially saved.