Invention Grant
- Patent Title: Memory array test method and system
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Application No.: US17884634Application Date: 2022-08-10
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Publication No.: US11715546B2Publication Date: 2023-08-01
- Inventor: Chien-Hao Huang , Katherine H. Chiang , Cheng-Yi Wu , Chung-Te Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/38 ; G11C11/16

Abstract:
A method of testing a non-volatile memory (NVM) array includes obtaining a current distribution of a subset of NVM cells of the NVM array, the current distribution including first and second portions corresponding to respective logically high and low states of the subset of NVM cells, programming an entirety of the NVM cells of the NVM array to one of the logically high or low states, determining an initial bit error rate (BER) by performing first and second pass/fail (P/F) tests on each NVM cell of the NVM array, and using the current distribution to adjust the initial BER rate. Each of obtaining the current distribution, programming the entirety of the NVM cells, and performing the first and second P/F tests is performed while the NVM array is heated to a target temperature.
Public/Granted literature
- US20220383974A1 MEMORY ARRAY TEST METHOD AND SYSTEM Public/Granted day:2022-12-01
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