Invention Grant
- Patent Title: Scan optimization using data selection across wordline of a memory array
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Application No.: US17946207Application Date: 2022-09-16
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Publication No.: US11715547B2Publication Date: 2023-08-01
- Inventor: Kishore Kumar Muchherla , Violante Moschiano , Sead Zildzic , Junwyn A. Lacsao , Paing Z. Htet
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- The original application number of the division: US17247633 2020.12.18
- Main IPC: G11C29/42
- IPC: G11C29/42 ; G11C29/44 ; G11C11/4074 ; G11C11/408 ; G11C29/50

Abstract:
A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.
Public/Granted literature
- US20230012644A1 SCAN OPTIMIZATION USING DATA SELECTION ACROSS WORDLINE OF A MEMORY ARRAY Public/Granted day:2023-01-19
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