Invention Grant
- Patent Title: Patterning material including silicon-containing layer and method for semiconductor device fabrication
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Application No.: US17213723Application Date: 2021-03-26
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Publication No.: US11715640B2Publication Date: 2023-08-01
- Inventor: Szu-Ping Tung , Chun-Kai Chen , Tze-Liang Lee , Yi-Nien Su
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/308
- IPC: H01L21/308 ; H01L21/027 ; H01L21/033 ; H01L21/311

Abstract:
In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.
Public/Granted literature
- US20220102150A1 PATTERNING MATERIAL INCLUDING SILICON-CONTAINING LAYER AND METHOD FOR SEMICONDUCTOR DEVICE FABRICATION Public/Granted day:2022-03-31
Information query
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