Invention Grant
- Patent Title: Methods of forming integrated circuit packages having adhesion layers over through vias
-
Application No.: US17338872Application Date: 2021-06-04
-
Publication No.: US11715717B2Publication Date: 2023-08-01
- Inventor: Hung-Chun Cho , Sih-Hao Liao , Yu-Hsiang Hu , Hung-Jui Kuo
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L23/48 ; H01L23/29 ; H01L25/065 ; H01L21/56 ; H01L23/538

Abstract:
In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.
Public/Granted literature
- US20220302066A1 Integrated Circuit Package and Method Public/Granted day:2022-09-22
Information query
IPC分类: