A buffer circuit, a frequency dividing circuit, and a communications device are disclosed. The buffer circuit includes a buffer, a first control circuit, and a second control circuit. The buffer is coupled to a frequency divider, and the buffer is configured to receive a first signal output by the frequency divider, and output a fourth signal by using an output terminal of the buffer circuit when driven by the first signal, where the first signal is obtained by the frequency divider by performing frequency division on a group of differential signals, and the differential signals include a second signal and a third signal. The first control circuit is configured to perform delay control on a rising edge of the fourth signal based on the second signal. The second control circuit is configured to perform delay control on a falling edge of the fourth signal based on the third signal.