A apparatus includes a memory cell region; a peripheral region adjacent to the memory cell region; first, second, third, fourth and fifth bit-lines arranged in numerical order and extending across the memory cell region and the peripheral region; and first, second and third bit-line contacts connecting with the first, third and fifth bit-lines in the peripheral region, respectively; wherein the first and second bit-line contacts are arranged adjacently without interposing the second bit-line therebetween; and wherein the second and third bit-line contacts are arranged adjacently with interposing the fourth bit-line therebetween.