Invention Grant
- Patent Title: Semiconductor memory devices having stacked structures therein that support high integration
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Application No.: US16985024Application Date: 2020-08-04
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Publication No.: US11716844B2Publication Date: 2023-08-01
- Inventor: Sangjae Lee , Jaehyung Kim , Dongseog Eun
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Myers Bigel, P.A.
- Priority: KR 20200013087 2020.02.04
- Main IPC: H10B43/27
- IPC: H10B43/27 ; H10B43/35 ; H10B43/40

Abstract:
A semiconductor device includes an upper stack structure extending on a lower stack structure, which extends on an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface, and a second upper electrode layer disposed adjacent a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.
Public/Granted literature
- US20210242235A1 SEMICONDUCTOR MEMORY DEVICES HAVING STACKED STRUCTURES THEREIN THAT SUPPORT HIGH INTEGRATION Public/Granted day:2021-08-05
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