Invention Grant
- Patent Title: Three-dimensional memory device and method
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Application No.: US17133964Application Date: 2020-12-24
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Publication No.: US11716855B2Publication Date: 2023-08-01
- Inventor: Chia Yu Ling , Chung-Te Lin , Katherine H. Chiang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H10B51/20
- IPC: H10B51/20 ; H01L29/06 ; G11C11/22 ; H10B51/10 ; H10B51/30

Abstract:
In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.
Public/Granted literature
- US20210375935A1 Three-Dimensional Memory Device and Method Public/Granted day:2021-12-02
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