- Patent Title: Method for performing smart semiconductor wafer defect calibration
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Application No.: US17233266Application Date: 2021-04-16
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Publication No.: US11719650B2Publication Date: 2023-08-08
- Inventor: Iyun Leu
- Applicant: ELITE SEMICONDUCTOR INC.
- Applicant Address: TW Zhudong Town
- Assignee: ELITE SEMICONDUCTOR INC.
- Current Assignee: ELITE SEMICONDUCTOR INC.
- Current Assignee Address: TW Zhudong Town
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: G01N21/95
- IPC: G01N21/95 ; H01L21/66 ; G06T7/00 ; G01N21/88 ; G06F30/398 ; G06F30/3323

Abstract:
A smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab are provided. The intelligent defect diagnosis method includes receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system. The method utilizes the precisely calibrated coordinate, the defect layout pattern, and the higher accurate calibrated defect size value. So, a more precise killer defect index can be generated with calibrated coordinate deviation calibration and defect size deviation calibration. When judging a defect relating to short circuit or open circuit failure probability, the defect failure result is more accurate and less incorrect judgment.
Public/Granted literature
- US20210231581A1 METHOD FOR PERFORMING SMART SEMICONDUCTOR WAFER DEFECT CALIBRATION Public/Granted day:2021-07-29
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