Invention Grant
- Patent Title: Unified bus architecture for a voltage regulator
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Application No.: US16917423Application Date: 2020-06-30
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Publication No.: US11720159B2Publication Date: 2023-08-08
- Inventor: Venkatesh Wadeyar , Vikas Lakhanpal , Preetam Charan Anand Tadeparthy
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Valerie M. Davis; Frank D. Cimino
- Priority: IN 1941026259 2019.07.01
- Main IPC: G06F1/28
- IPC: G06F1/28 ; G06F13/42

Abstract:
In described examples, a voltage regulator includes a processor. A register bank is coupled to the processor. A logic block is coupled to the processor and to the register bank. The logic block receives frames. The processor programs the logic block and the register bank based on at least one of the frames.
Public/Granted literature
- US20210004072A1 UNIFIED BUS ARCHITECTURE FOR A VOLTAGE REGULATOR Public/Granted day:2021-01-07
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