Methods, systems, and devices for compressed logical-to-physical mapping for a memory bypass for error detection and correction are described. A memory device may include error detection and correction circuitry for detecting and correcting errors in data that is read from a memory array of the memory device. To reduce read latencies, the memory device may include bypass circuitry that enables it to transmit the data to the host device before or during error detection. If the memory device determines that the data is erroneous, the memory device may transmit an alert to the host device concurrently with or after transmitting the data. The memory device may perform error correction on the data and store corrected data in a register. Based on receiving an alert, the host device may issue one or more additional read commands to re-read the data from the memory bank or read the corrected data from the register.