Invention Grant
- Patent Title: Debugging dataflow computer architectures
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Application No.: US17991390Application Date: 2022-11-21
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Publication No.: US11720475B2Publication Date: 2023-08-08
- Inventor: Skyler Arron Windh , Tony M. Brewer , Patrick Estep
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F11/36 ; G06F9/30

Abstract:
Disclosed in some examples are methods, systems, devices, and machine-readable mediums that use parallel hardware execution with software co-simulation to enable more advanced debugging operations on data flow architectures. Upon a halt to execution of a program thread, a state of the tiles that are executing the thread are saved and offloaded from the HTF to a host system. A developer may then examine this state on the host system to debug their program. Additionally, the state may be loaded into a software simulator that simulates the HTF hardware. This simulator allows for the developer to step through the code and to examine values to find bugs.
Public/Granted literature
- US20230079727A1 DEBUGGING DATAFLOW COMPUTER ARCHITECTURES Public/Granted day:2023-03-16
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