Invention Grant
- Patent Title: Multi-level cache security
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Application No.: US16882380Application Date: 2020-05-22
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Publication No.: US11720495B2Publication Date: 2023-08-08
- Inventor: Abhijeet Ashok Chachad , David Matthew Thompson , Naveen Bhoria
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instmments Incorporated
- Current Assignee: Texas Instmments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Michael T. Gabrik; Frank D. Cimino
- Main IPC: G06F12/0811
- IPC: G06F12/0811 ; G06F9/46 ; G06F12/0817 ; G06F12/0831 ; G06F12/1081 ; G06F12/14 ; G06F21/79 ; G06F12/128 ; G06F12/0864

Abstract:
In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The CPU is arranged to execute program instructions to manipulate data in at least a first or second secure context. Each of the first and second caches stores a secure code for indicating the at least first or second secure contexts by which data for a respective cache line is received. The first and second level caches maintain coherency in response to comparing the secure codes of respective lines of cache and executing a cache coherency operation in response.
Public/Granted literature
- US20200371927A1 MULTI-LEVEL CACHE SECURITY Public/Granted day:2020-11-26
Information query
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