- Patent Title: Reconfigurable cache architecture and methods for cache coherency
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Application No.: US17504594Application Date: 2021-10-19
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Publication No.: US11720496B2Publication Date: 2023-08-08
- Inventor: Elad Raz
- Applicant: Next Silicon Ltd.
- Applicant Address: IL Tel Aviv
- Assignee: Next Silicon Ltd
- Current Assignee: Next Silicon Ltd
- Current Assignee Address: IL Givatayim
- Main IPC: G06F12/0815
- IPC: G06F12/0815 ; G06F12/0893

Abstract:
A method for cache coherency in a reconfigurable cache architecture is provided. The method includes receiving a memory access command, wherein the memory access command includes at least an address of a memory to access; determining at least one access parameter based on the memory access command; and determining a target cache bin for serving the memory access command based in part on the at least one access parameter and the address.
Public/Granted literature
- US20220100660A1 RECONFIGURABLE CACHE ARCHITECTURE AND METHODS FOR CACHE COHERENCY Public/Granted day:2022-03-31
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