A gate driving circuit and a display device including the same are disclosed. The gate driving circuit includes signal transmitters receiving a start pulse, a shift clock, a charge/discharge clock, a back-bias clock, a high-potential driving voltage, and a low-potential reference voltage, and connected in a cascade structure. An Nth (N is a positive integer) signal transmitter of the signal transmitters includes a first control node; a second control node; a first controller controlling charging and discharging of the first control node by using at least one transistor to which the back-bias clock is inputted; a second controller controlling charging and discharging of the second control node; a first output buffer outputting a carry pulse in response to voltages of the first and second control nodes; and a second output buffer outputting a gate pulse.